21 lines
380 B
Makefile
21 lines
380 B
Makefile
ECHO = @echo
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GCC = g++
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RM = @rm -f
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CCFLAGS = -c -g -ansi -pedantic -Wall #optimization?
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OBJETS = $(SRC:.cpp=.o)
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SRC = $(wildcard *.cpp)
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EXE = deployer
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LIBRARIES =
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$(EXE) : $(OBJETS)
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$(ECHO) "-Linking $(EXE)-"
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$(GCC) -o $@ $^ $(LIBRARIES)
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%.o:%.cpp
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$(ECHO) "-Compilation $<- "
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$(GCC) $(CCFLAGS) -o $@ $<
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.PHONY: clean
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clean:
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$(ECHO) "-Cleaning-"
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$(RM) $(OBJETS) $(EXE)
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